There is a frequent demand for smaller devices with more memory. Some efforts have been initiated in resistive memory as a mechanism for creating more memory in less space. Resistive memory systems use a resistive element that can change and maintain the value of its resistivity based on applied conditions. For example, a high resistive state may be used to represent a logical ‘1’ while a low resistive state may be used to represent a logical ‘0’.
Such resistive memory cells are often constructed as an array of memory cells, with each cell being placed on intersecting conductive lines. To set or read the state of a particular memory cell within the array, the conductive lines connecting to that memory cell are selected. The selected lines can have various electrical conditions applied in order to set or read the resistive state of the targeted memory cell.
For example, a voltage may be applied to the appropriate conductive lines to read the state of a target memory cell. This voltage causes an electric current to flow through the target memory cell. Based on the value of this electric current, the resistive state of the memory cell can be determined. Electric current, however, will also flow through the conductive lines to unselected memory cells and may adversely affect the sensing operation that measures the value of the electric current flowing through the target memory cell. This current is often referred to as a sneak current. It is desirable to design a memory cell and array architecture that avoids the sneak current issue.